Interrupt handling

Hi Andy,

A long time back (must be about 5 or 6 years ago) I remember a
discussion about interrupt handling, and in particular what would be
appropriate for systems that used level triggered interrupts rather than
edge triggered.

The edge triggered case is easy since we just get an interrupt and we
don't need to clear the cause down before we leave the ISR - thus making
it easy to send the interrupt messages to device servers.

I seem to remember that there may have been a few different solutions to
the level triggerred case (one was some interpretted code handled within
the kernel that a device server would be able to register when it
initialized).

I've been playing with another microcontroller families recently (Atmel
AVRs) writting an LGPL'd embedded OS and have ended up with a similar
sort of design to VSTa where I want to handle all interrupts within
normally scheduled threads and hit on a slightly different solution - I
need this because pulling a 1.5k packet out of an ethernet chip with an
8 bit micro can take serveral ms and I don't want to screw up my UART
code. Rather than trying to clear the interrupt cause down in the ISR
(which is what I started doing), my latest tack is to temporarily
disable the interrupt within the interrupt management unit (effectively
the PIC) which allows me to leave the ISR, but without upsetting the
state of the interrupting device. My threads then re-enable the
interrupt within the IMU once they've handled the interrupting event.

Anyway, the question is: How general a mechanism is this? I know that
this works for several micro families, but I don't know if there are any
subtle gotcha's that would cause this to fail on other micros or
interrupt units.

                                Regards,
                                Dave
Received on Sun May 28 03:45:09 2000