RE: Miscellaneous comments and questions

-----Original Message-----
From: Andy Valencia [mailto:vandys@zendo.com]
Sent: Friday, February 16, 2001 5:22 PM
To: Sandro Magi
Cc: vsta@zendo.com
Subject: Re: Miscellaneous comments and questions

[...]
Or if somebody has a good utility I could attach to CGI, I'd be happy to
look into it.

glint
[..]
your philosophy essay references a preference for memory remapping in the
tasker and kernel if im not mistaken. I have some curiousity about your
present day view looking back on what is presently in place; Do you still
feel that you have a relative freedom from copy operations particularly from
one io buffer to the other?
I wouldn't know how to obtain a reference that gives an idea of cycles
involved with block copying vs. hardware remapping; nor do I quite
understand the role of all the devices in the mmu of intel, and I understand
that sun4 and sun3 architectures have a software mmu.
Suns have context switch registers, and in faq I ran across regarding linux
there was a mention that the linux kernel can be boiled down to about 3
context entries whereas slowaris can easily usurp the majority of these
context slots and roll the cache entries off the edge, the cost of exporting
the context maps is apparently quite high.
Is it typical practice to write queus of block operations that are linked
together and serviced in a chain under a single context where possible?
Possibly even a single instruction to dispatch with many merged pipelined
block operations with multiple segments being written in the same refresh?
Does vsta for intel have equivalent hardware support for context switching
or would this be a benefit of having a hardware MMU that can recv and handle
context info via the caching and paging hardware?
Does vsta context switch particularly better or worse that you had hoped in
any areas? What sort of span of time are we to expect on a page fault or
context switch operation ?
If I were to indulge in wanton memory remapping excercises on the intel
platform, what sort of alignment or block minimum addressing is available to
the hardware mmu? What keen microcode can we take advantage of that would
take the place of small asm byte moves? Is this essentially stuff that is
pushed onto gcc for scheduling, pipelining? how much faster is it to call a
p5 4M block move remap operation than the equivalent [1-4]k block remaps?
can motherboard resources be taken advantage of for asynchronous
move/copy/remapping operations? Do certain chipsets make a big difference
in these kind of areas or is everyone vending pretty much identical
featuresets throughout the entire cost range of a given bus classification.
(by this I mean, are all pci32 busses the same general speed, all eisa, all
isa, all bridge devices all created pretty much equal to their competitors,
no matter what kind of registers you can tweak)
sorry for the deluge. One will never get a good feel for the hardware
contours living and working around high level languages

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Received on Fri Feb 16 19:50:12 2001