Optimisations.

Hi All,

I've not really had much chance to look at optimisations for the VSTa
kernel recently, but if anyone's interested in performance work the
following WEB page has pointers to some very interesting papers on the L3
microkernel:

        http://www.inf.tu-dresden.de/%7Emh1/prj/lites-on-l3/l3.html

This is an extremely fast x86 kernel, and whilst both it and the MIT
exokernel take the view that OS's should be more CPU specific (instead of
proving the virtual machine interface as provided by VSTa) there are some
tremendous insights into some possible optimisations of the CPU specific
stuff in any kernel (and I guess the portable stuff too).

Someone might like to look at the TLB miss performance figures (the
performance hits are huge) of the 486 and Pentium! Certainly this might
explain why I got so confused about some of the optimisation work I did on
the VSTa kernel earlier last year (occasionally I'd take one step
backwards for what on paper seemed to be a step forwards).

In addition, at the moment (unless 1.5 changes this yet - I've not had the
opportunity to look yet), VSTa doesn't use segmentation apart from to
provide user/kernel separation. The cost of segment register loads and
reloads on entry to or exit from the kernel is very high (over 40 clocks
on a 486) - I think it ought to be possible to run use one DPL 3 segment
for both user and kernel use and avoid this cost. As far as security goes
the kernel's memory is marked as supervisor access only so only the
kernel's CPL 0 code segment will grant access to kernel data.

                                Regards,
                                Dave
Received on Wed Jan 10 14:18:37 1996